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Using Cacheline Reuse Characteristics for Prefetcher Throttling
https://uec.repo.nii.ac.jp/records/290
https://uec.repo.nii.ac.jp/records/2908139a576-251f-45e1-b362-94a0d04bc03d
名前 / ファイル | ライセンス | アクション |
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Item type | 学術雑誌論文 / Journal Article(1) | |||||
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公開日 | 2012-12-01 | |||||
タイトル | ||||||
言語 | en | |||||
タイトル | Using Cacheline Reuse Characteristics for Prefetcher Throttling | |||||
言語 | ||||||
言語 | eng | |||||
キーワード | ||||||
言語 | en | |||||
主題Scheme | Other | |||||
主題 | microarchitecture | |||||
キーワード | ||||||
言語 | en | |||||
主題Scheme | Other | |||||
主題 | cache | |||||
キーワード | ||||||
言語 | en | |||||
主題Scheme | Other | |||||
主題 | prefetch | |||||
資源タイプ | ||||||
資源タイプ識別子 | http://purl.org/coar/resource_type/c_6501 | |||||
資源タイプ | journal article | |||||
著者 |
Irie, Hidetsugu
× Irie, Hidetsugu× Miyoshi, Takefumi× Honjo, Goki× Hiraki, Kei× Yoshinaga, Tsutomu |
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著者ID | ||||||
内容記述タイプ | Other | |||||
内容記述 | 1000070506732 | |||||
著者ID | ||||||
内容記述タイプ | Other | |||||
内容記述 | 1000020238348 | |||||
著者ID | ||||||
内容記述タイプ | Other | |||||
内容記述 | 1000060210738 | |||||
内容記述 | ||||||
内容記述タイプ | Other | |||||
内容記述 | One of the significant issues of processor architecture is to overcome memory latency. Prefetching can greatly improve cache performance, but it has the drawback of cache pollution, unless its aggressiveness is properly set. Several techniques that have been proposed for prefetcher throttling use accuracy as a metric, but their robustness were not sufficient because of the variations in programs’ working set sizes and cache capacities. In this study, we revisit prefetcher throttling from the viewpoint of data lifetime. Exploiting the characteristics of cache line reuse, we propose Cache-Convection-Control-based Prefetch Optimization Plus (CCCPO+),which enhances the feedback algorithm of our previous CCCPO. Evaluation results showed that this novel approach achieved a 30% improvement over no prefetching in the geometric mean of the SPEC CPU 2006 benchmark suite with 256KB LLC, 1.8% over the latest prefetcher throttling, ity compared to related works, while lowering the hardware cost. | |||||
書誌情報 |
IEICE transactions on information and systems 巻 E95-D, 号 12, p. 2928-2938, 発行日 2012-12 |
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出版者 | ||||||
出版者 | THE INSTITUTE OF ELECTRONICS, INFORMATION AND COMMUNICATION ENGINEERS | |||||
ISSN | ||||||
収録物識別子タイプ | ISSN | |||||
収録物識別子 | 09168532 | |||||
権利 | ||||||
権利情報 | Copyright (c) 2012 IEICE | |||||
関連サイト | ||||||
識別子タイプ | URI | |||||
関連識別子 | https://search.ieice.org/index.html | |||||
著者版フラグ | ||||||
出版タイプ | VoR | |||||
出版タイプResource | http://purl.org/coar/version/c_970fb48d4fbd8a85 |