{"created":"2023-05-15T08:38:03.301782+00:00","id":290,"links":{},"metadata":{"_buckets":{"deposit":"c7b233e7-765d-4160-84fe-86bb2caa2a35"},"_deposit":{"created_by":3,"id":"290","owners":[3],"pid":{"revision_id":0,"type":"depid","value":"290"},"status":"published"},"_oai":{"id":"oai:uec.repo.nii.ac.jp:00000290","sets":["6"]},"author_link":["6426","6424","6423","6427","6425"],"item_10001_biblio_info_7":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicIssueDates":{"bibliographicIssueDate":"2012-12","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"12","bibliographicPageEnd":"2938","bibliographicPageStart":"2928","bibliographicVolumeNumber":"E95-D","bibliographic_titles":[{"bibliographic_title":"IEICE transactions on information and systems"}]}]},"item_10001_description_4":{"attribute_name":"著者ID","attribute_value_mlt":[{"subitem_description":"1000070506732","subitem_description_type":"Other"},{"subitem_description":"1000020238348","subitem_description_type":"Other"},{"subitem_description":"1000060210738","subitem_description_type":"Other"}]},"item_10001_description_6":{"attribute_name":"内容記述","attribute_value_mlt":[{"subitem_description":"One of the significant issues of processor architecture is to overcome memory latency. Prefetching can greatly improve cache performance, but it has the drawback of cache pollution, unless its aggressiveness is properly set. Several techniques that have been proposed for prefetcher throttling use accuracy as a metric, but their robustness were not sufficient because of the variations in programs’ working set sizes and cache capacities. In this study, we revisit prefetcher throttling from the viewpoint of data lifetime. Exploiting the characteristics of cache line reuse, we propose Cache-Convection-Control-based Prefetch Optimization Plus (CCCPO＋),which enhances the feedback algorithm of our previous CCCPO. Evaluation results showed that this novel approach achieved a 30% improvement over no prefetching in the geometric mean of the SPEC CPU 2006 benchmark suite with 256KB LLC, 1.8% over the latest prefetcher throttling, ity compared to related works, while lowering the hardware cost.","subitem_description_type":"Other"}]},"item_10001_publisher_8":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"THE INSTITUTE OF ELECTRONICS, INFORMATION AND COMMUNICATION ENGINEERS"}]},"item_10001_relation_17":{"attribute_name":"関連サイト","attribute_value_mlt":[{"subitem_relation_type_id":{"subitem_relation_type_id_text":"https://search.ieice.org/index.html","subitem_relation_type_select":"URI"}}]},"item_10001_rights_15":{"attribute_name":"権利","attribute_value_mlt":[{"subitem_rights":"Copyright (c) 2012 IEICE"}]},"item_10001_source_id_9":{"attribute_name":"ISSN","attribute_value_mlt":[{"subitem_source_identifier":"09168532 ","subitem_source_identifier_type":"ISSN"}]},"item_10001_version_type_20":{"attribute_name":"著者版フラグ","attribute_value_mlt":[{"subitem_version_resource":"http://purl.org/coar/version/c_970fb48d4fbd8a85","subitem_version_type":"VoR"}]},"item_creator":{"attribute_name":"著者","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Irie, Hidetsugu","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Miyoshi, Takefumi","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Honjo, Goki","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Hiraki, Kei","creatorNameLang":"en"}],"nameIdentifiers":[{}]},{"creatorNames":[{"creatorName":"Yoshinaga, Tsutomu","creatorNameLang":"en"}],"nameIdentifiers":[{}]}]},"item_files":{"attribute_name":"ファイル情報","attribute_type":"file","attribute_value_mlt":[{"accessrole":"open_date","date":[{"dateType":"Available","dateValue":"2016-09-15"}],"displaytype":"detail","filename":"9000000652.pdf","filesize":[{"value":"1.7 MB"}],"format":"application/pdf","licensetype":"license_note","mimetype":"application/pdf","url":{"label":"9000000652.pdf","url":"https://uec.repo.nii.ac.jp/record/290/files/9000000652.pdf"},"version_id":"5932f7c8-23c6-4c2c-aa2c-009982cc4a6f"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"microarchitecture","subitem_subject_language":"en","subitem_subject_scheme":"Other"},{"subitem_subject":"cache","subitem_subject_language":"en","subitem_subject_scheme":"Other"},{"subitem_subject":"prefetch","subitem_subject_language":"en","subitem_subject_scheme":"Other"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"eng"}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourcetype":"journal article","resourceuri":"http://purl.org/coar/resource_type/c_6501"}]},"item_title":"Using Cacheline Reuse Characteristics for Prefetcher Throttling","item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"Using Cacheline Reuse Characteristics for Prefetcher Throttling","subitem_title_language":"en"}]},"item_type_id":"10001","owner":"3","path":["6"],"pubdate":{"attribute_name":"公開日","attribute_value":"2012-12-01"},"publish_date":"2012-12-01","publish_status":"0","recid":"290","relation_version_is_last":true,"title":["Using Cacheline Reuse Characteristics for Prefetcher Throttling"],"weko_creator_id":"3","weko_shared_id":3},"updated":"2023-05-15T09:40:58.973901+00:00"}