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An Efficient and Scalable Implementation of Sliding-Window Aggregate Operator on FPGA
https://uec.repo.nii.ac.jp/records/1929
https://uec.repo.nii.ac.jp/records/19291db6c73f-3c8b-4818-97ea-d27f6d490181
| 名前 / ファイル | ライセンス | アクション |
|---|---|---|
9090000218.pdf (971.9 kB)
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| Item type | 会議発表論文 / Conference Paper(1) | |||||
|---|---|---|---|---|---|---|
| 公開日 | 2016-09-15 | |||||
| タイトル | ||||||
| タイトル | An Efficient and Scalable Implementation of Sliding-Window Aggregate Operator on FPGA | |||||
| 言語 | en | |||||
| 言語 | ||||||
| 言語 | eng | |||||
| キーワード | ||||||
| 言語 | en | |||||
| 主題Scheme | Other | |||||
| 主題 | data stream processing | |||||
| キーワード | ||||||
| 言語 | en | |||||
| 主題Scheme | Other | |||||
| 主題 | disordered data | |||||
| キーワード | ||||||
| 言語 | en | |||||
| 主題Scheme | Other | |||||
| 主題 | sliding window | |||||
| キーワード | ||||||
| 言語 | en | |||||
| 主題Scheme | Other | |||||
| 主題 | aggregation | |||||
| キーワード | ||||||
| 言語 | en | |||||
| 主題Scheme | Other | |||||
| 主題 | pane-based query evaluation | |||||
| キーワード | ||||||
| 言語 | en | |||||
| 主題Scheme | Other | |||||
| 主題 | FPGA | |||||
| 資源タイプ | ||||||
| 資源タイプ識別子 | http://purl.org/coar/resource_type/c_5794 | |||||
| 資源タイプ | conference paper | |||||
| 著者 |
Yasin, Oge
× Yasin, Oge× Masato, Yoshimi× Takefumi, Miyoshi× Hideyuki, Kawashima× Hidetsugu, Irie× Tsutomu, Yoshinaga |
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| 内容記述 | ||||||
| 内容記述タイプ | Other | |||||
| 内容記述 | This paper presents an efficient and scalable implementation of an FPGA-based accelerator for sliding-window aggregates over disordered data streams. With an increasing number of overlapping sliding-windows, the window aggregates have a serious scalability issue, especially when it comes to implementing them in parallel processing hardware (e.g., FPGAs). To address the issue, we propose a resource-ef?cient, scalable, and order-agnostic hardware design and its implementation by examining and integrating two key concepts, called Window-ID and Pane, which are originally proposed for software implementation, respectively. Evaluation results show that the proposed implementation scales well compared to the previous FPGA implementation in terms of both resource consumption and performance. The proposed design is fully pipelined and our implementation can process out-of-order data items, or tuples, at wire speed up to 200 million tuples per second. | |||||
| 書誌情報 |
en : First International Symposium on Computing and Networking (CANDAR'13) p. 112-121, 発行日 2013-12 |
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| 出版者 | ||||||
| 出版者 | IEEE | |||||
