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  1. 会議発表論文

Wire-Speed Implementation of Sliding-Window Aggregate Operator over Out-of-Order Data Streams

https://uec.repo.nii.ac.jp/records/1928
https://uec.repo.nii.ac.jp/records/1928
769806a6-0666-4db8-8ef5-ccdfaa023034
名前 / ファイル ライセンス アクション
9090000217.pdf 9090000217.pdf (203.0 kB)
Item type 会議発表論文 / Conference Paper(1)
公開日 2016-09-15
タイトル
言語 en
タイトル Wire-Speed Implementation of Sliding-Window Aggregate Operator over Out-of-Order Data Streams
言語
言語 eng
キーワード
言語 en
主題Scheme Other
主題 data stream processing
キーワード
言語 en
主題Scheme Other
主題 disordered data
キーワード
言語 en
主題Scheme Other
主題 sliding window
キーワード
言語 en
主題Scheme Other
主題 aggregation
キーワード
言語 en
主題Scheme Other
主題 stream punctuation
キーワード
言語 en
主題Scheme Other
主題 FPGA
資源タイプ
資源タイプ識別子 http://purl.org/coar/resource_type/c_5794
資源タイプ conference paper
著者 Yasin, Oge

× Yasin, Oge

WEKO 6397

en Yasin, Oge

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Masato, Yoshimi

× Masato, Yoshimi

WEKO 6398

en Masato, Yoshimi

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Takefumi, Miyoshi

× Takefumi, Miyoshi

WEKO 6399

en Takefumi, Miyoshi

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Hideyuki, Kawashima

× Hideyuki, Kawashima

WEKO 6400

en Hideyuki, Kawashima

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Hidetsugu, Irie

× Hidetsugu, Irie

WEKO 6401

en Hidetsugu, Irie

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Tsutomu, Yoshinaga

× Tsutomu, Yoshinaga

WEKO 6402

en Tsutomu, Yoshinaga

Search repository
内容記述
内容記述タイプ Other
内容記述 This paper shows the design and evaluation of an FPGA-based accelerator for sliding-window aggregation over data streams with out-of-order data arrival. We propose an order-agnostic hardware implementation technique for windowing operators based on a one-pass query evaluation strategy called Window-ID, which is originally proposed for software implementation. The proposed implementation succeeds to process out-of-order data items, or tuples, at wire speed due to the simultaneous evaluations of overlapping sliding-windows. In order to verify the effectiveness of the proposed approach, we have also implemented an experimental system as a case study. Our experiments demonstrate that the proposed accelerator with a network interface achieves an effective throughput around 760 Mbps or equivalently nearly 6 million tuples per second, by fully utilizing the available bandwidth of the network interface.
書誌情報 en : IEEE 7th International Symposium on Embedded Multicore/Many-core SoCs (MCSoC-13)

p. 55-60, 発行日 2013-09
出版者
出版者 IEEE
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