@inproceedings{oai:uec.repo.nii.ac.jp:00001928,
 author = {Yasin, Oge and Masato, Yoshimi and Takefumi, Miyoshi and Hideyuki, Kawashima and Hidetsugu, Irie and Tsutomu, Yoshinaga},
 book = {IEEE 7th International Symposium on Embedded Multicore/Many-core SoCs (MCSoC-13)},
 month = {Sep},
 note = {This paper shows the design and evaluation of an FPGA-based accelerator for sliding-window aggregation over data streams with out-of-order data arrival. We propose an order-agnostic hardware implementation technique for windowing operators based on a one-pass query evaluation strategy called Window-ID, which is originally proposed for software implementation. The proposed implementation succeeds to process out-of-order data items, or tuples, at wire speed due to the simultaneous evaluations of overlapping sliding-windows. In order to verify the effectiveness of the proposed approach, we have also implemented an experimental system as a case study. Our experiments demonstrate that the proposed accelerator with a network interface achieves an effective throughput around 760 Mbps or equivalently nearly 6 million tuples per second, by fully utilizing the available bandwidth of the network interface.},
 pages = {55--60},
 publisher = {IEEE},
 title = {Wire-Speed Implementation of Sliding-Window Aggregate Operator over Out-of-Order Data Streams},
 year = {2013}
}