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An Efficient Path Setup for a Hybrid Photonic Network-on-Chip
https://uec.repo.nii.ac.jp/records/289
https://uec.repo.nii.ac.jp/records/289d7e559d2-c1c6-4c9e-930b-7ce29041c56f
| 名前 / ファイル | ライセンス | アクション |
|---|---|---|
9000000559.pdf (205.0 kB)
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| Item type | 学術雑誌論文 / Journal Article(1) | |||||
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| 公開日 | 2012-07-11 | |||||
| タイトル | ||||||
| タイトル | An Efficient Path Setup for a Hybrid Photonic Network-on-Chip | |||||
| 言語 | en | |||||
| 言語 | ||||||
| 言語 | eng | |||||
| キーワード | ||||||
| 言語 | en | |||||
| 主題Scheme | Other | |||||
| 主題 | nanophotonics | |||||
| キーワード | ||||||
| 言語 | en | |||||
| 主題Scheme | Other | |||||
| 主題 | photonic NoC | |||||
| キーワード | ||||||
| 言語 | en | |||||
| 主題Scheme | Other | |||||
| 主題 | predictive switching | |||||
| キーワード | ||||||
| 言語 | en | |||||
| 主題Scheme | Other | |||||
| 主題 | multicore processors | |||||
| 資源タイプ | ||||||
| 資源タイプ識別子 | http://purl.org/coar/resource_type/c_6501 | |||||
| 資源タイプ | journal article | |||||
| 著者 |
Cisse, Ahmadou Dit ADI
× Cisse, Ahmadou Dit ADI× Hiroki, Matsutani× Michihiro, Koibuchi× Hidetsugu, Irie× Takefumi, Miyoshi× Tsutomu, Yoshinaga |
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| 著者ID | ||||||
| 内容記述タイプ | Other | |||||
| 内容記述 | 1000070611135 | |||||
| 著者ID | ||||||
| 内容記述タイプ | Other | |||||
| 内容記述 | 1000040413926 | |||||
| 著者ID | ||||||
| 内容記述タイプ | Other | |||||
| 内容記述 | 1000070506732 | |||||
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| 内容記述タイプ | Other | |||||
| 内容記述 | 1000060210738 | |||||
| 内容記述 | ||||||
| 内容記述タイプ | Other | |||||
| 内容記述 | Electrical network-on-chip (NoC) faces critical challenges in meeting the high performanceand low power consumption requirements for future multicore processors interconnection. Re- cent tremendous advances in CMOS compatible optical components give the potential for photonicsto deliver an efficient NoC performance at an acceptable energy cost. However, the lackof in flight processing and buffering of optical data made the realization of a fully optical NoCcomplicated. A hybrid architecture which uses optical high bandwidth transfer and an electricalcontrol network can take advantage of both interconnection methods to offer an efficientperformance-per-watt infrastructure to connect multicore processors and system-on-chip (SoC).In this paper, we propose a predictive switching and a reservation based path setup techniquesto reduce the path setup latency of such hybrid photonic network-on-chip (HPNoC). By usingthese techniques, it is possible to reduce the latency for end-to-end communication in a HPNoCimproving its overall performance. In the simulation, we use a cycle accurate simulator underuniform, neighbor, and bitreversal traffic patterns for a 64-node torus topology. The resultsshow that the proposed techniques considerably improve the overall latency of HPNoC. | |||||
| 書誌情報 |
International Journal of Networking and Computing 巻 1, 号 2, p. 244-259, 発行日 2011-07-11 |
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| 出版者 | ||||||
| 出版者 | IJNC編集委員会 | |||||
| ISSN | ||||||
| 収録物識別子タイプ | ISSN | |||||
| 収録物識別子 | 21852839 | |||||
| 関連サイト | ||||||
| 識別子タイプ | URI | |||||
| 関連識別子 | http://ijnc.org/ | |||||
| 著者版フラグ | ||||||
| 出版タイプ | VoR | |||||
| 出版タイプResource | http://purl.org/coar/version/c_970fb48d4fbd8a85 | |||||
