@article{oai:uec.repo.nii.ac.jp:00000289,
 author = {Cisse, Ahmadou Dit   ADI and Hiroki, Matsutani and Michihiro, Koibuchi and Hidetsugu, Irie and Takefumi, Miyoshi and Tsutomu, Yoshinaga},
 issue = {2},
 journal = {International Journal of Networking and Computing},
 month = {Jul},
 note = {1000070611135, 1000040413926, 1000070506732, 1000060210738, Electrical network-on-chip (NoC) faces critical challenges in meeting the high performanceand low power consumption requirements for future multicore processors interconnection. Re- cent tremendous advances in CMOS compatible optical components give the potential for photonicsto deliver an efficient NoC performance at an acceptable energy cost. However, the lackof in flight processing and buffering of optical data made the realization of a fully optical NoCcomplicated. A hybrid architecture which uses optical high bandwidth transfer and an electricalcontrol network can take advantage of both interconnection methods to offer an efficientperformance-per-watt infrastructure to connect multicore processors and system-on-chip (SoC).In this paper, we propose a predictive switching and a reservation based path setup techniquesto reduce the path setup latency of such hybrid photonic network-on-chip (HPNoC). By usingthese techniques, it is possible to reduce the latency for end-to-end communication in a HPNoCimproving its overall performance. In the simulation, we use a cycle accurate simulator underuniform, neighbor, and bitreversal traffic patterns for a 64-node torus topology. The resultsshow that the proposed techniques considerably improve the overall latency of HPNoC.},
 pages = {244--259},
 title = {An Efficient Path Setup for a Hybrid Photonic Network-on-Chip},
 volume = {1},
 year = {2011}
}