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{"_buckets": {"deposit": "734c0622-f9dc-40a6-bcc3-2cbacf7ab55d"}, "_deposit": {"created_by": 3, "id": "1925", "owners": [3], "pid": {"revision_id": 0, "type": "depid", "value": "1925"}, "status": "published"}, "_oai": {"id": "oai:uec.repo.nii.ac.jp:00001925", "sets": ["2"]}, "author_link": ["6383", "6384", "6385", "6386"], "control_number": "1925", "item_10003_biblio_info_30": {"attribute_name": "書誌情報", "attribute_value_mlt": [{"bibliographicIssueDates": {"bibliographicIssueDate": "2012-09", "bibliographicIssueDateType": "Issued"}, "bibliographicPageEnd": "91", "bibliographicPageStart": "84", "bibliographic_titles": [{"bibliographic_title": "IEEE 6th International Symposium on Embedded Multicore SoCs (MCSoC-12)", "bibliographic_titleLang": "en"}]}]}, "item_10003_description_29": {"attribute_name": "内容記述", "attribute_value_mlt": [{"subitem_description": "A novel merging network architecture is proposed for a handshake join operator in order to achieve much higher data throughput than ever before. Handshake join is a highly parallelized algorithm for window-based stream joins. Result collection performed by a merging network is a significant design issue for the handshake join operator because the merging network becomes an overwhelming bottleneck for scalable performance. To address the issue, an adaptive merging network is proposed for hardware implementation of the algorithm. The proposed architecture is implemented on an FPGA and it is evaluated in terms of the hardware resource usage, the maximum clock frequency, and the performance. Experimental results demonstrate up to 16.3 times higher throughput than nested loops-style join implementation without dropping any tuples. To the best of our knowledge, this is the best performance for handshake join operator implemented on an FPGA.", "subitem_description_type": "Other"}]}, "item_10003_publisher_31": {"attribute_name": "出版者", "attribute_value_mlt": [{"subitem_publisher": "IEEE"}]}, "item_creator": {"attribute_name": "著者", "attribute_type": "creator", "attribute_value_mlt": [{"creatorNames": [{"creatorName": "Yasin, Oge", "creatorNameLang": "en"}], "nameIdentifiers": [{"nameIdentifier": "6383", "nameIdentifierScheme": "WEKO"}]}, {"creatorNames": [{"creatorName": "Takefumi, Miyoshi", "creatorNameLang": "en"}], "nameIdentifiers": [{"nameIdentifier": "6384", "nameIdentifierScheme": "WEKO"}]}, {"creatorNames": [{"creatorName": "Hideyuki, Kawashima", "creatorNameLang": "en"}], "nameIdentifiers": [{"nameIdentifier": "6385", "nameIdentifierScheme": "WEKO"}]}, {"creatorNames": [{"creatorName": "Tsutomu, Yoshinaga", "creatorNameLang": "en"}], "nameIdentifiers": [{"nameIdentifier": "6386", "nameIdentifierScheme": "WEKO"}]}]}, "item_files": {"attribute_name": "ファイル情報", "attribute_type": "file", "attribute_value_mlt": [{"accessrole": "open_date", "date": [{"dateType": "Available", "dateValue": "2016-09-15"}], "displaytype": "detail", "download_preview_message": "", "file_order": 0, "filename": "9090000045.pdf", "filesize": [{"value": "100.9 kB"}], "format": "application/pdf", "future_date_message": "", "is_thumbnail": false, "licensetype": "license_free", "mimetype": "application/pdf", "size": 100900.0, "url": {"label": "9090000045.pdf", "url": "https://uec.repo.nii.ac.jp/record/1925/files/9090000045.pdf"}, "version_id": "5eab0709-0bcf-4637-bd62-08e8712a911b"}]}, "item_keyword": {"attribute_name": "キーワード", "attribute_value_mlt": [{"subitem_subject": "window-based stream join", "subitem_subject_language": "en", "subitem_subject_scheme": "Other"}, {"subitem_subject": "Handshake join", "subitem_subject_language": "en", "subitem_subject_scheme": "Other"}, {"subitem_subject": "merging network", "subitem_subject_language": "en", "subitem_subject_scheme": "Other"}, {"subitem_subject": "FPGA", "subitem_subject_language": "en", "subitem_subject_scheme": "Other"}]}, "item_language": {"attribute_name": "言語", "attribute_value_mlt": [{"subitem_language": "eng"}]}, "item_resource_type": {"attribute_name": "資源タイプ", "attribute_value_mlt": [{"resourcetype": "conference paper", "resourceuri": "http://purl.org/coar/resource_type/c_5794"}]}, "item_title": "Design and Implementation of a Merging Network Architecture for Handshake Join Operator on FPGA", "item_titles": {"attribute_name": "タイトル", "attribute_value_mlt": [{"subitem_title": "Design and Implementation of a Merging Network Architecture for Handshake Join Operator on FPGA", "subitem_title_language": "en"}]}, "item_type_id": "10003", "owner": "3", "path": ["2"], "permalink_uri": "https://uec.repo.nii.ac.jp/records/1925", "pubdate": {"attribute_name": "PubDate", "attribute_value": "2016-09-15"}, "publish_date": "2016-09-15", "publish_status": "0", "recid": "1925", "relation": {}, "relation_version_is_last": true, "title": ["Design and Implementation of a Merging Network Architecture for Handshake Join Operator on FPGA"], "weko_shared_id": -1}
  1. 会議発表論文

Design and Implementation of a Merging Network Architecture for Handshake Join Operator on FPGA

https://uec.repo.nii.ac.jp/records/1925
https://uec.repo.nii.ac.jp/records/1925
b5d36100-7e03-4e66-9844-81e6586afe85
名前 / ファイル ライセンス アクション
9090000045.pdf 9090000045.pdf (100.9 kB)
Item type 会議発表論文 / Conference Paper(1)
公開日 2016-09-15
タイトル
言語 en
タイトル Design and Implementation of a Merging Network Architecture for Handshake Join Operator on FPGA
言語
言語 eng
キーワード
言語 en
主題Scheme Other
主題 window-based stream join
キーワード
言語 en
主題Scheme Other
主題 Handshake join
キーワード
言語 en
主題Scheme Other
主題 merging network
キーワード
言語 en
主題Scheme Other
主題 FPGA
資源タイプ
資源タイプ識別子 http://purl.org/coar/resource_type/c_5794
資源タイプ conference paper
著者 Yasin, Oge

× Yasin, Oge

WEKO 6383

en Yasin, Oge

Search repository
Takefumi, Miyoshi

× Takefumi, Miyoshi

WEKO 6384

en Takefumi, Miyoshi

Search repository
Hideyuki, Kawashima

× Hideyuki, Kawashima

WEKO 6385

en Hideyuki, Kawashima

Search repository
Tsutomu, Yoshinaga

× Tsutomu, Yoshinaga

WEKO 6386

en Tsutomu, Yoshinaga

Search repository
内容記述
内容記述タイプ Other
内容記述 A novel merging network architecture is proposed for a handshake join operator in order to achieve much higher data throughput than ever before. Handshake join is a highly parallelized algorithm for window-based stream joins. Result collection performed by a merging network is a significant design issue for the handshake join operator because the merging network becomes an overwhelming bottleneck for scalable performance. To address the issue, an adaptive merging network is proposed for hardware implementation of the algorithm. The proposed architecture is implemented on an FPGA and it is evaluated in terms of the hardware resource usage, the maximum clock frequency, and the performance. Experimental results demonstrate up to 16.3 times higher throughput than nested loops-style join implementation without dropping any tuples. To the best of our knowledge, this is the best performance for handshake join operator implemented on an FPGA.
書誌情報 en : IEEE 6th International Symposium on Embedded Multicore SoCs (MCSoC-12)

p. 84-91, 発行日 2012-09
出版者
出版者 IEEE
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