{"_buckets": {"deposit": "b3aed263-cc2f-4179-9177-c32b7141ac7b"}, "_deposit": {"created_by": 3, "id": "1923", "owners": [3], "pid": {"revision_id": 0, "type": "depid", "value": "1923"}, "status": "published"}, "_oai": {"id": "oai:uec.repo.nii.ac.jp:00001923", "sets": ["2"]}, "author_link": ["6377", "6376", "6378", "6375"], "item_10003_biblio_info_30": {"attribute_name": "書誌情報", "attribute_value_mlt": [{"bibliographicIssueDates": {"bibliographicIssueDate": "2011-09-09", "bibliographicIssueDateType": "Issued"}, "bibliographicPageEnd": "495", "bibliographicPageStart": "490", "bibliographic_titles": [{}, {"bibliographic_title": "21st International Conference on Field Programmable Logic and Applications", "bibliographic_titleLang": "en"}]}]}, "item_10003_description_29": {"attribute_name": "内容記述", "attribute_value_mlt": [{"subitem_description": "This paper proposes a processor architecture for DR-SPE,a dynamic reconfigurable stream processing engine. DR-SPE is specialpurposehardware for stream data processing, which achieves highprocessing performance by exploiting parallelism in the target query.It also handles query registration and execution order of operationsat runtime. Available operations in DR-SPE are the same as those inStreams on Wires. In this paper, DR-SPE is implemented on a FPGAXC6VLX240T-1, and its performance is evaluated. The results of theevaluation show that DR-SPE achieves register modification within 506 sec when the configuration path is driven at 1 Mbps, which is notachieved by Streams on Wires. DR-SPE also achieves flexibility and cansupport complicated queries by providing 10 10 operation units tiledonto an FPGA. DR-SPE achieves comparable operation throughput withStreams on Wires at the expense of requiring more LUTs.", "subitem_description_type": "Other"}]}, "item_10003_publisher_31": {"attribute_name": "出版者", "attribute_value_mlt": [{"subitem_publisher": "IEEE"}]}, "item_creator": {"attribute_name": "著者", "attribute_type": "creator", "attribute_value_mlt": [{"creatorNames": [{"creatorName": "Takefumi, Miyoshi", "creatorNameLang": "en"}], "nameIdentifiers": [{"nameIdentifier": "6375", "nameIdentifierScheme": "WEKO"}]}, {"creatorNames": [{"creatorName": "Hideyuki, Kawashima", "creatorNameLang": "en"}], "nameIdentifiers": [{"nameIdentifier": "6376", "nameIdentifierScheme": "WEKO"}]}, {"creatorNames": [{"creatorName": "Yuta, Terada", "creatorNameLang": "en"}], "nameIdentifiers": [{"nameIdentifier": "6377", "nameIdentifierScheme": "WEKO"}]}, {"creatorNames": [{"creatorName": "Tsutomu, Yoshinaga", "creatorNameLang": "en"}], "nameIdentifiers": [{"nameIdentifier": "6378", "nameIdentifierScheme": "WEKO"}]}]}, "item_files": {"attribute_name": "ファイル情報", "attribute_type": "file", "attribute_value_mlt": [{"accessrole": "open_date", "date": [{"dateType": "Available", "dateValue": "2016-09-15"}], "displaytype": "detail", "download_preview_message": "", "file_order": 0, "filename": "9000000567.pdf", "filesize": [{"value": "356.6 kB"}], "format": "application/pdf", "future_date_message": "", "is_thumbnail": false, "licensetype": "license_free", "mimetype": "application/pdf", "size": 356600.0, "url": {"label": "9000000567.pdf", "url": "https://uec.repo.nii.ac.jp/record/1923/files/9000000567.pdf"}, "version_id": "e722b95d-2b6b-40b3-95ff-9994a12a2bcd"}]}, "item_language": {"attribute_name": "言語", "attribute_value_mlt": [{"subitem_language": "eng"}]}, "item_resource_type": {"attribute_name": "資源タイプ", "attribute_value_mlt": [{"resourcetype": "conference paper", "resourceuri": "http://purl.org/coar/resource_type/c_5794"}]}, "item_title": "A Coarse Grain Reconfigurable Processor Architecture for Stream Processing Engine", "item_titles": {"attribute_name": "タイトル", "attribute_value_mlt": [{"subitem_title": "A Coarse Grain Reconfigurable Processor Architecture for Stream Processing Engine", "subitem_title_language": "en"}]}, "item_type_id": "10003", "owner": "3", "path": ["2"], "permalink_uri": "https://uec.repo.nii.ac.jp/records/1923", "pubdate": {"attribute_name": "公開日", "attribute_value": "2016-09-15"}, "publish_date": "2016-09-15", "publish_status": "0", "recid": "1923", "relation": {}, "relation_version_is_last": true, "title": ["A Coarse Grain Reconfigurable Processor Architecture for Stream Processing Engine"], "weko_shared_id": 3}