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A Coarse Grain Reconfigurable Processor Architecture for Stream Processing Engine
https://uec.repo.nii.ac.jp/records/1923
https://uec.repo.nii.ac.jp/records/192355030f93-1d12-450b-bf36-a54dc35c9c39
名前 / ファイル | ライセンス | アクション |
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Item type | 会議発表論文 / Conference Paper(1) | |||||
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公開日 | 2016-09-15 | |||||
タイトル | ||||||
言語 | en | |||||
タイトル | A Coarse Grain Reconfigurable Processor Architecture for Stream Processing Engine | |||||
言語 | ||||||
言語 | eng | |||||
資源タイプ | ||||||
資源タイプ識別子 | http://purl.org/coar/resource_type/c_5794 | |||||
資源タイプ | conference paper | |||||
著者 |
Takefumi, Miyoshi
× Takefumi, Miyoshi× Hideyuki, Kawashima× Yuta, Terada× Tsutomu, Yoshinaga |
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内容記述 | ||||||
内容記述タイプ | Other | |||||
内容記述 | This paper proposes a processor architecture for DR-SPE,a dynamic reconfigurable stream processing engine. DR-SPE is specialpurposehardware for stream data processing, which achieves highprocessing performance by exploiting parallelism in the target query.It also handles query registration and execution order of operationsat runtime. Available operations in DR-SPE are the same as those inStreams on Wires. In this paper, DR-SPE is implemented on a FPGAXC6VLX240T-1, and its performance is evaluated. The results of theevaluation show that DR-SPE achieves register modification within 506 sec when the configuration path is driven at 1 Mbps, which is notachieved by Streams on Wires. DR-SPE also achieves flexibility and cansupport complicated queries by providing 10 10 operation units tiledonto an FPGA. DR-SPE achieves comparable operation throughput withStreams on Wires at the expense of requiring more LUTs. | |||||
書誌情報 |
en : 21st International Conference on Field Programmable Logic and Applications p. 490-495, 発行日 2011-09-09 |
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出版者 | ||||||
出版者 | IEEE |