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スーパースカラ・プロセッサの設計と機能シミュレーション
https://uec.repo.nii.ac.jp/records/8281
https://uec.repo.nii.ac.jp/records/8281df843d38-7a92-4749-bef2-081d0cfd31ba
Item type | 紀要論文 / Departmental Bulletin Paper(1) | |||||
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公開日 | 1997-12-01 | |||||
タイトル | ||||||
タイトル | スーパースカラ・プロセッサの設計と機能シミュレーション | |||||
タイトル | ||||||
言語 | en | |||||
タイトル | Design and Simulation of a Superscalar Processor | |||||
言語 | ||||||
言語 | jpn | |||||
資源タイプ | ||||||
資源タイプ識別子 | http://purl.org/coar/resource_type/c_6501 | |||||
資源タイプ | departmental bulletin paper | |||||
アクセス権 | ||||||
アクセス権 | metadata only access | |||||
アクセス権URI | http://purl.org/coar/access_right/c_14cb | |||||
著者 |
安藤, 穣
× 安藤, 穣× 阿部, 公輝× Ando, Yutaka× Abe, Koki |
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書誌情報 |
電気通信大学紀要 en : Bulletin of the University of Electro-Communications 巻 10, 号 2, p. 63-69, 発行日 1997-12 |
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ISSN | ||||||
収録物識別子タイプ | ISSN | |||||
収録物識別子 | 09150935 | |||||
書誌レコードID | ||||||
収録物識別子タイプ | NCID | |||||
収録物識別子 | AN10016842 |