@phdthesis{oai:uec.repo.nii.ac.jp:00008521,
 author = {TRAN, THI THU HUONG},
 month = {2017-04-24},
 note = {2016, This thesis aims to enhance nonlinear characteristics of single-electron (SE) logic devices and fabricate SE devices.
　For the first main goal, the nonlinear characteristics of SE logic gates including SE four-junction inverter (SE FJI) and SE NAND gates were improved by using the numerical method. With a continuous input signal, the SE FJI and SE NAND gates have a disadvantage of gradual switches between high and low output levels, resulting in unclear decisions about output states in the transition region. To overcome this disadvantage, the switching was enhanced to become sharp by adding an SE input discretizer (ID) between an input terminal and a main device (SE logic device). The ID discretizes the continuous input signal into a discrete intermediate signal which is then forwarded into the main device. Parameters of the ID were calculated from the conditions of the Coulomb blockade (CB) phenomena and confirmed from Monte-Carlo simulation using SIMON program to achieve the sharp switching at the designed threshold voltage. On the one hand, the addition of one ID to each input of SE logic device exhibited the sharp switching. Namely, an SE FJI with an ID (ID-FJI) achieved the sharp switching and its unclear region was reduced to 0.011 times in comparison with the solo FJI. An SE NAND gate with two separate IDs (ID-NAND) exhibited the sharp switches and its unclear regions were decreased to 0.33 times in comparison with the solo NAND gate. On the other hand, the addition of two serially-cascaded IDs to the SE FJI (2ID-FJI) formed a hysteretic inverter. In addition, stochastic resonance was enhanced remarkably by using the 2ID-FJI, which was equivalent to the use of an ideal hysteretic inverter.
　For the second main goal, SE devices were realized by using gold nanoparitcles (Au NPs). Drain, source, and gate electrodes were fabricated by combining standard electron beam lithography (EBL) and evaporation techniques. The technical difficulty in the fabrication process was reduced by forming the wide (_ 200 nm) gap between the drain and source electrodes. After that, arrays of small tunnel junctions were formed by dropping solutions of Au NPs. Characteristics like capacitively-coupled single-electron transistor (C-SET) and resistively-coupled SET (R-SET) were confirmed at 77 K. Moreover, the CB gap was not only observed but also modulated by applying the gate voltage at room temperature (287 K).},
 school = {電気通信大学},
 title = {Enhanced nonlinear electric properties and applications based on the Coulomb blockade phenomena in arrays of small tunnel junctions},
 year = {}
}