@article{oai:uec.repo.nii.ac.jp:00006811,
 author = {奈良岡, 雅人 and Naraoka, Masato and 鈴木, 貢 and Suzuki, Mitsugu and 楯岡, 孝道 and Tateoka, Takamichi and 阿部, 公輝 and Abe, Koki},
 issue = {2},
 journal = {電気通信大学紀要},
 month = {Jan},
 note = {An equipment for logic design laboratory was developed using an FPGA (Field ProgrammableGate Array). By meas of CAD (Computer-Aided Design) software along with the equipment,students can perform experiments for designing and implementing real hardware circuits by wiringlogic symbols. The equipment we call FPGA Logic Trainer has several advantages such that misconnectionsdue to broken wires do not occur, and erroneous designs by students can never crashthe equipment. It is compact and inexpensive, in spite of accomodating a large number of gatesenough for implementing large-scale logic circuts. In this paper, we describe the development ofthe FPGA Logic Trainer, present an example of the experiments using the equipment, and evaulateit as a logic design laboratory tool.},
 pages = {215--218},
 title = {FPGA を使った論理回路用実験装置},
 volume = {15},
 year = {2003},
 yomi = {ナラオカ, マサト and スズキ, ミツグ and タテオカ, タカミチ and アベ, コウキ}
}