@inproceedings{oai:uec.repo.nii.ac.jp:00001927,
 author = {Yicheng, Guan and Cisse, Ahmadou Dit ADI and Takefumi, Miyoshi and Michihiro, Koibuchi and Hidetsugu, Irie and Tsutomu, Yoshinaga},
 book = {IEEE 6th International Symposium on Embedded Multicore SoCs (MCSoC-12)},
 month = {Sep},
 note = {As the number of core integration on a single die grows, buffers consume significant energy, and occupy chip area. A bufferless deflection outing that eliminates router’s input port buffers can considerably help saving energy and chip area while providing similar performance of xisting buffered routing, especially for low-to-medium network loads. However when congestion increases, the bufferless frequently causes flits deflections, and misrouting leading to a degradation of network performance. In this paper, we propose IRT(Injection Rate Throttling), a  ocal throttling mechanism that reduces deflection and misrouting for high-load bufferless networks. IRT provides injection rate control independently for each network node, allowing to reduce network congestion. Our simulation results based on a cycle-accurate simulator show that using IRT, IRT reduces average transmission latency by 8.65% compared to traditional bufferless routing.},
 pages = {37--44},
 publisher = {IEEE},
 title = {Throttling Control for Bufferless Routing in On-Chip Networks},
 year = {2012}
}